High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits
Type:
Journal
Info:
Scientific Reports 7, Article number: 1368 (2017)
Date:
2017-01-10
Author Information
| Name | Institution |
|---|---|
| Tsung-Ta Wu | National Nano Device Labs |
| Wen-Hsien Huang | National Nano Device Labs |
| Chih-Chao Yang | National Nano Device Labs |
| Hung-Chun Chen | National Nano Device Labs |
| Tung-Ying Hsieh | National Nano Device Labs |
| Wei-Sheng Lin | National Tsing Hua University |
| Ming-Hsuan Kao | National Chiao Tung University |
| Chiu-Hao Chen | National Nano Device Labs |
| Jie-Yi Yao | National Nano Device Labs |
| Yi-Ling Jian | National Nano Device Labs |
| Chiung-Chih Hsu | National Nano Device Labs |
| Kun-Lin Lin | National Nano Device Labs |
| Chang-Hong Shen | National Nano Device Labs |
| Yu-Lun Chueh | National Tsing Hua University |
| Jia-Ming Shieh | National Nano Device Labs |
Films
Film/Plasma Properties
Substrates
Notes
| 1086 |