High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits

Type:
Journal
Info:
Scientific Reports 7, Article number: 1368 (2017)
Date:
2017-01-10

Author Information

Name Institution
Tsung-Ta WuNational Nano Device Labs
Wen-Hsien HuangNational Nano Device Labs
Chih-Chao YangNational Nano Device Labs
Hung-Chun ChenNational Nano Device Labs
Tung-Ying HsiehNational Nano Device Labs
Wei-Sheng LinNational Tsing Hua University
Ming-Hsuan KaoNational Chiao Tung University
Chiu-Hao ChenNational Nano Device Labs
Jie-Yi YaoNational Nano Device Labs
Yi-Ling JianNational Nano Device Labs
Chiung-Chih HsuNational Nano Device Labs
Kun-Lin LinNational Nano Device Labs
Chang-Hong ShenNational Nano Device Labs
Yu-Lun ChuehNational Tsing Hua University
Jia-Ming ShiehNational Nano Device Labs

Films

Plasma Al2O3


Film/Plasma Properties

Substrates

Notes

1086